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標題Title: Synthesis and Design of Parameter Extractors for Low-Power Pre-computation-Based Content-addressable Memory Using Gate-Block Selection Algorithm
作者Authors: 曹正曄
上傳單位Department: 電子工程系
上傳時間Date: 2010-7-13
上傳者Author: 曹正曄
審核單位Department: 電子工程系
審核老師Teacher: 陳順智
檔案類型Categories: 課堂報告In-class Report
關鍵詞Keyword: CAM, PB-CAM, Low-Power
摘要Abstract: Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in fast search time, it also significantly increases power consumption. In this paper, we propose a gateblock selection algorithm, which can synthesize a proper parameter
extractor of the pre-computation-based CAM (PB-CAM) to improve the efficiency for specific applications such as embedded systems. Through experimental results, we found that our approach effectively reduces the number of comparison operations for specific data types (ranging from 19.24% to 27.42%) compared with the 1’s count approach. We used Synopsys Nanosim to estimate the power consumption in TSMC 0.35um CMOS process.
Compared to the 1’s count PB-CAM, our proposed PB-CAM achieves 17.72% to 21.09% in power reduction for specific data types.

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2010_7_d8b4b57f.ppt 406Kb ppt 1157 27
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